|
Geunyeol YuPh.D. Candidate
rgyen [dot] postech.ac.kr |
I am a Ph.D. candidate in the Software Verification Laboratory at POSTECH, under the supervision of Kyungmin Bae. My research focuses on developing secure and reliable systems using formal methods such as model checking, rewriting logic, and SMT solving.
Research Interests
- Model checking of Signal Temporal Logic (STL) properties in cyber-physical systems
- Formal specification and analysis of Trusted Execution Environments (TEEs)
- Development of an extensible framework integrating rewriting logic and SMT solving
Software
Publications
-
SMT-Based Robust Model Checking for Signal Temporal Logic
Jia Lee, Geunyeol Yu, Kyungmin Bae
Science of Computer Programming, 2025
paper | project
-
Formal Specification of Trusted Execution Environment APIs
Geunyeol Yu, Seunghyun Chae, Kyungmin Bae, Sungkun Moon
International Conference on Fundamental Approaches to Software Engineering (FASE) , 2024
paper | project | slides
-
A Flexible Framework for Integrating Maude and SMT Solvers Using Python
Geunyeol Yu, Kyungmin Bae
International Workshop on Rewriting Logic and its Applications (WRLA) , 2024
paper | project
-
STLmc: Robust STL Model Checking of Hybrid Systems Using SMT
Geunyeol Yu, Jia Lee, Kyungmin Bae
International Conference on Computer Aided Verification (CAV) , 2022
paper | project
Academic Activities
- Artifact evaluation committee member
Honors
- Research Subsidies for Ph.D. Candidates, National Research Foundation of Korea, 2024
- Best paper/presentation award, WRLA, 2024
- POSTECH CSE Paper Award, 2023
- National Science & Technology Scholarship, 2012-2015, 2018