Geunyeol Yu Ph.D. Student POSTECH, South Korea rgyen [dot] postech.ac.kr Google Scholar

I am a Ph.D. student in the Software Verification Laboratory at POSTECH, under the supervision of Kyungmin Bae. My research focuses on formal analysis and techniques, based on model checking and rewrite theory, aimed at developing secure and reliable computer systems.

Research Interests

• Model checking of signal temporal logic (STL) properties of cyber-physical systems.
• Formal specification and analysis of trusted execution environment (TEE) APIs using rewrite theory.

Software

• Maude-SE
• STLmc

Publications

• A Flexible Framework for Integrating Maude and SMT Solvers Using Python
  Geunyeol Yu, Kyungmin Bae
  International Workshop on Rewriting Logic and its Applications (WRLA), 2024
  paper | project

• Formal Specification of Trusted Execution Environment APIs
  Geunyeol Yu, Seunghyun Chae, Kyungmin Bae, Sungkun Moon
  International Conference on Fundamental Approaches to Software Engineering (FASE), 2024
  paper | slides | project

• STLmc: Robust STL Model Checking of Hybrid Systems Using SMT
  Geunyeol Yu, Jia Lee, Kyungmin Bae
  International Conference on Computer Aided Verification (CAV), 2022
  paper | project

• Efficient SMT-based Model Checking for Signal Temporal Logic
  Jia Lee, Geunyeol Yu, Kyungmin Bae
  International Conference on Automated Software Engineering (ASE), 2021
  paper | project

• Maude-SE: a Tight Integration of Maude and SMT solvers
  Geunyeol Yu, Kyungmin Bae
  International Workshop on Rewriting Logic and its Applications (WRLA), 2020
  paper | project

Honors

• Research Subsidies for Ph.D. Candidates, National Research Foundation of Korea, 2024
• Best paper/presentation award, WRLA, 2024
• POSTECH CSE Paper Award, 2023